Senior FPGA Verification Engineer

About the role

We are seeking a Senior FPGA Verification Engineer with 6‑9 years of hands‑on functional verification experience to join a highly technical team developing complex FPGA‑based systems. The role focuses on creating and executing verification strategies for both block‑level and top‑level FPGA designs, collaborating closely with RTL designers and system engineers.

Key responsibilities

• Design, develop and maintain SystemVerilog/UVM verification environments for FPGA components and full systems.
• Create detailed verification plans and run directed and constrained‑random test scenarios.
• Develop assertions and functional coverage models to ensure thorough verification.
• Execute simulation‑based verification using industry‑standard tools and perform root‑cause debugging of functional issues.
• Integrate Verification IP, scoreboards, checkers and reference models.
• Support FPGA bring‑up, validation and debugging on evaluation boards.
• Review RTL, verification code and test plans for quality and completeness.
• Mentor junior engineers and promote best practices in FPGA verification.
• Drive regression runs, coverage closure, sign‑off and release activities.

Required profile

• Bachelor’s or Master’s degree in Electronics, Electrical, Computer Engineering or a related field.
• 6–9 years of practical experience in functional verification of complex FPGA designs.
• Proven ability to work collaboratively with RTL designers and system teams.

Required skills

• SystemVerilog and UVM.
• Verilog and VHDL.
• Cadence Xcelium or equivalent simulation tools.
• Xilinx Vivado.
• FPGA verification methodologies, testbench architecture, assertions and functional coverage.
• Debugging, root‑cause analysis and verification planning.
• Verification IP integration, scoreboards, checkers, reference models.
• Knowledge of AXI, AXI‑Stream, DDR and SPI interfaces.