Senior Verification Engineer

About the role

AST SpaceMobile is developing a global cellular broadband network in space and is looking for a Senior Verification Engineer to lead FPGA verification efforts. The role involves creating robust verification environments, collaborating with RTL designers, and ensuring high‑quality FPGA implementations for both commercial and government missions.

Key responsibilities

• Design and maintain SystemVerilog/UVM testbenches for block‑level and top‑level FPGA designs.
• Develop verification plans, constrained‑random tests, assertions, and functional coverage models.
• Run simulations using Xcelium, Questa, or VCS and analyse results to debug functional issues.
• Integrate verification IPs, scoreboards, checkers, and reference models.
• Support FPGA bring‑up, validation, and debugging on evaluation boards.
• Review RTL and verification code for completeness and quality.
• Mentor junior engineers and promote best practices in verification.
• Manage regression runs, coverage closure, and release sign‑off.

Required profile

• Bachelor’s or Master’s degree in Electronics, Electrical, Computer Engineering or related field.
• 6‑9 years of hands‑on functional verification experience.
• Strong analytical and debugging abilities with excellent communication skills.
• Self‑driven, detail‑oriented and able to work across cross‑functional teams.

Required skills

• SystemVerilog, Verilog, VHDL
• UVM methodology
• Cadence Xcelium, Questa, VCS simulators
• Xilinx Vivado
• Debug tools such as SimVision
• Scripting in Python, Tcl, Shell
• Version control with Git
• Knowledge of AXI, AXI‑Stream, DDR, SPI interfaces